This invention relates generally to CMOS latch circuits. More particularly, the present invention relates to a method and apparatus for reliably placing the latch in a preferred logic state upon power-up to the full supply voltage level.
A CMOS cross-coupled latch that reliably powers up in a predictable state (one side high, one side low, with a single-sided output reflecting the preferred logic state) can be very useful in an integrated circuit. The preferred logic state latch circuit output may be buffered and driven globally to many destinations on an integrated circuit. The latch circuit output can be used to properly initialize certain nodes in the integrated circuit so that it is ready for normal operation.
A typical cross-coupled latch is shown in FIG. 1, including cross-coupled P-channel transistors M1 and M2, and cross-coupled N-channel transistors M3 and M4. The sources of transistors M1 and M2 are coupled together and to a source of power supply voltage V.sub.DD, which is typically five, 3.3, or three volts. The sources of transistors M3 and M4 are coupled together and to a source of power supply voltage V.sub.SS, which is typically ground voltage, zero volts, but can be a negative power supply voltage such as minus five volts.
As can be seen in the labels associated with transistors M1-M4 of FIG. 1, by placing relatively "strong" and "weak" devices connecting to the appropriate nodes, the latch can be reliably depended upon to power-up in the preferred state. A "strong" device is defined as a device whose W/L ratio is greater than a "weak" device. Consequently, the "strong" device will have a greater saturation current than a "weak" device, as is well known in the art. In the latch shown in FIG. 1, a "High" output node coupled to the drains of transistors M1 and M3, and the gates of transistors M2 and M4 will usually power-up in a logic high state, and a "Low" output node coupled to the drains of transistors M2 and M4, and the gates of transistors M1 and M3 will usually power-up in a logic low state.
Conventional methods to design the preferred-state latch shown in FIG. 1 usually involve varying the gate widths (the "W" in the W/L ratio) of the respective devices to dictate the relative device strength. The gate widths of the strong devices (M1 and M4) are designed to be larger than that of the weak devices (M2 and M3). Before power-up all circuit nodes are at the same voltage. As V.sub.DD rises from the same potential as V.sub.SS to that of the specified power supply range, the latch can be expected to power-up in the correct state. This is due to the intrinsic ability of the strong devices to conduct more current (because of the greater W/L ratio) than can be conducted by the weak devices, thereby influencing the logic state of the latch. Once a small differential voltage between the output nodes is realized the inherent positive feedback of this circuit configuration results in the attainment of the full proper logic state.
While the above describes the desirable outcome, the preferred or "designed-in" power-up logic state is not always attained in a real-world circuit. Before a voltage differential in the direction of the preferred state occurs, possibly while the latch circuit devices are still in sub-threshold conduction, the conventional approach can result in the wrong data state due to the influence of parasitic gate-to-source/drain overlap capacitance terms (C.sub.GS or C.sub.GD). The gate-to-source capacitance terms may provide capacitive coupling in the opposite direction required to attain the preferred state. These coupling terms could provide negative feedback, and not the desired positive feedback. The negative feedback, in turn, can reduce the reliability of the latch to consistently power-up in the expected state for all possible combinations of temperature, voltage, power supply ramp rate, or processing variations.
What is desired, therefore, is a preferred state power-up latch that will reliably enter into the preferred state over a wide range of environmental and electrical operating conditions.